`timescale 1ns/1ps

module tb_dds_ctrl;
    localparam work_clk = 100_000_000;  // 300 MHz
    localparam ttl_freq = 500;         // 1 kHz

    reg clk;
    reg rst_n;
    wire ttl;
    wire [7:0] sin_ref;
    wire [7:0] cos_ref;

    // 实例化 DUT
    dds_ctrl #(
        .work_clk(work_clk),
        .ttl_freq(ttl_freq)
    ) uut (
        .clk(clk),
        .rst_n(rst_n),
        .ttl(ttl),
        .sin_ref(sin_ref),
        .cos_ref(cos_ref)
    );

    // 100MHz 时钟生成：周期 10ns
    always #5 clk = ~clk;

    initial begin
        clk = 0;
        rst_n = 0;

        #100;
        rst_n = 1;

        #1_000_000;

        $stop;
    end

endmodule
